This invention relates to the manufacture of advanced semiconductor devices, particularly advanced CMOS integrated devices in which metal gate electrodes are used.
With the continued scaling of CMOS devices to smaller dimensions, the gate dielectrics of these devices have been reduced to thicknesses well below 20 Å. This in turn has led to greatly increased gate leakage currents and diffusion of dopants from the polysilicon gate structures (often referred to as the poly depletion effect).
Metal gates are now being used to mitigate the poly depletion effect and control the leakage current, and thus to ensure electrical performance in highly integrated CMOS devices. A metal gate is typically formed by a “replacement gate” process, in which a dummy polysilicon gate is first formed and then removed, and a metal gate formed in its place. The metal gate may span both n+ and p+ gate areas and comprise a single metal with a midgap work function. Alternatively, the replacement gate may comprise two metals with different work functions, in the space previously occupied by the n+ and p+ polysilicon gates respectively.
As an example of the present state of the art, U.S. patent application Publication No. 2003/0119292 of Lee et al., “Integration of dual workfunction metal gate CMOS devices,” describes a replacement-gate process for forming a metal gate in which a doped polysilicon gate is formed and then removed, leaving an open trench; a bulk metal layer is deposited in the trench and then planarized to yield a metal gate. This approach may present manufacturing problems in two ways. First, a very narrow gate structure (corresponding to a very short channel length, perhaps less than 70 nm) results in a high-aspect-ratio trench which may be difficult to fill without introducing a void in the metal. Second, a metal planarization process (typically chemical-mechanical polishing or CMP) is susceptible to dishing effects which cause nonuniformities in the metal thickness (and thus in the height of the metal gate).
It is also desirable to provide a silicided contact for the metal gate electrode. Accordingly, there is a need for a metal gate CMOS device with a silicide contact thereto, which is easily manufacturable and applicable to both a midgap replacement gate and a dual-metal replacement gate.